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A low spur CMOS phase-locked loop with wide tuning range for CMOS Image Sensor.
Zhiqing Chen
Qi Zhang
Ning Wang
Dunshan Yuan
Guohong Li
Hui Wang
Songlin Feng
Published in:
ASICON (2013)
Keyphrases
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cmos image sensor
dynamic range
single chip
low power consumption
solid state
parallel processing
phase locked loop
processing capabilities
low power
power consumption
low cost
image enhancement
high volume
image sensor
fully integrated
real time
high speed
control system
cmos technology
data streams
image processing