An Optimized Deep-Learning-Based Low Power Approximate Multiplier Design.
M. UsharaniB. SakthivelS. Gayathri PriyaT. NagalakshmiJ. ShirishaPublished in: Comput. Syst. Sci. Eng. (2023)
Keyphrases
- low power
- deep learning
- single chip
- power consumption
- low cost
- high speed
- low power consumption
- vlsi architecture
- logic circuits
- gate array
- digital signal processing
- cmos technology
- power dissipation
- power reduction
- general purpose
- probabilistic model
- mixed signal
- vlsi circuits
- unsupervised learning
- super resolution
- nm technology