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A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors.
Shoaib Akram
Alexandros Papakonstantinou
Rakesh Kumar
Deming Chen
Published in:
Int. J. Reconfigurable Comput. (2010)
Keyphrases
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multicore processors
high speed
hardware implementation
low cost
computing power
real time
general purpose
software architecture
dynamic reconfiguration
response time
signal processing
data flow
field programmable gate array
high end