A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS.
Ahmad DarabihaAnthony Chan CarusoneFrank R. KschischangPublished in: CICC (2007)
Keyphrases
- min sum
- ldpc codes
- low density parity check
- distributed source coding
- successive approximation
- turbo codes
- distributed video coding
- decoding algorithm
- error correction
- lower bound
- low complexity
- np hard
- analog to digital converter
- motion compensation
- low power
- channel coding
- power consumption
- goal programming
- min cut
- motion compensated
- message passing
- video compression
- error resilience
- video codec
- temporal correlation
- rate allocation
- data envelopment analysis
- error resilient
- motion estimation