The design of a low power asynchronous multiplier.
Yijun LiuStephen B. FurberPublished in: ISLPED (2004)
Keyphrases
- low power
- single chip
- power consumption
- low cost
- logic circuits
- low power consumption
- gate array
- high speed
- vlsi architecture
- digital signal processing
- power dissipation
- wireless transmission
- delay insensitive
- ultra low power
- real time
- vlsi circuits
- mixed signal
- high power
- cmos technology
- power reduction
- multi channel
- video sequences