A low-power digital design of all digital PLL for 2.4G wireless communication applications.
Bin ZhaoDan Lei YanPublished in: ISIC (2016)
Keyphrases
- low power
- mixed signal
- wireless communication
- wireless transmission
- single chip
- power consumption
- high speed
- vlsi circuits
- low cost
- cmos image sensor
- low power consumption
- gate array
- circuit design
- multi channel
- digital signal processing
- logic circuits
- short range
- power dissipation
- vlsi architecture
- analog to digital converter
- cmos technology
- power reduction
- wireless channels
- wireless networks
- wireless sensor networks
- communication networks
- computer simulation