A ring-VCO-based sub-sampling PLL CMOS circuit with -119 dBc/Hz phase noise and 0.73 ps jitter.

Kenta Sogo Akihiro Toya Takamaro Kikkawa

Published in: ESSCIRC (2012)

Keyphrases

high speed
circuit design
analog vlsi
delay insensitive
low power
low voltage
cmos technology
vlsi circuits
frame rate
power consumption
sampling algorithm
power dissipation
chip design
high frame rate
random sampling
monte carlo
algebraic structure
sample size
frequency response
low cost
frequency band
nm technology