Sign in
Power optimized PLL implementation in 180nm CMOS technology.
Sreehari Rao Patri
Pavankumarsharma Devulapalli
Dhananjay Kewale
Omkar Asbe
K. S. R. Krishna Prasad
Published in:
VDAT (2014)
Keyphrases
</>
cmos technology
power consumption
low power
power dissipation
silicon on insulator
spl times
low voltage
parallel processing
power management
low cost
mixed signal
high speed
data center
image processing
hardware implementation
clock frequency
multimedia