A Two-Stage CMOS OTA with Load-Pole Cancellation.

Ajmal Vadakkan Kayyil Pavan Kumar Ramakrishna OnnLim Yong David J. Allstot Howard C. Yang

Published in: ISCAS (2019)

Keyphrases

low voltage
load balancing
low cost
analog vlsi
high speed
power consumption
low power
vlsi circuits
multiple output
delay insensitive
circuit design
image sensor
load balance
power supply
neural network
design considerations
computer vision
learning algorithm