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Area Efficient & High Performance Word Line Segmented Architecture in 7nm FinFET SRAM Compiler.
Vinay Kumar
Neeraj Kapoor
Sudhir Kumar
Monila Juneja
Amit Khanuja
Published in:
VLSI Design (2019)
Keyphrases
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cost effective
power consumption
management system
highly optimized
low power
high efficiency
general purpose
high speed
n gram
computation intensive