Power-efficient VLSI implementation of bitstream parsing in H.264/AVC decoder.
Ke XuOliver Chiu-sing ChoyCheong-fat ChanKong-Pang PunPublished in: ISCAS (2006)
Keyphrases
- bitstream
- bit rate
- vlsi implementation
- error resilient
- error concealment
- coding scheme
- rate allocation
- video decoder
- scalable video coding
- video quality
- compression algorithm
- coded video
- macroblock
- video codec
- pixel domain
- video coding
- video transmission
- compressed domain
- low complexity
- rate distortion
- error resilience
- video coding standard
- coding efficiency
- inter frame
- compressed images
- compressed video
- visual quality
- motion vectors
- computational complexity
- packet loss
- motion estimation
- image compression
- motion compensated prediction
- scalable video
- bit plane
- fir filters
- data compression
- coding method
- image processing