A low power high speed accumulator for DDFS applications.

Michael Chappell Alistair McEwan

Published in: ISCAS (2) (2004)

Keyphrases

low power
high speed
hough transform
single chip
power consumption
real time
wireless transmission
low cost
vlsi circuits
low power consumption
mixed signal
frame rate
cmos technology
vlsi architecture
high power
logic circuits
delay insensitive
power reduction
digital signal processing
signal processor
gate array