Hardware model checking competition 2017.
Armin BiereTom van DijkKeijo HeljankoPublished in: FMCAD (2017)
Keyphrases
- model checking
- temporal logic
- temporal properties
- automated verification
- formal verification
- model checker
- finite state
- formal specification
- reachability analysis
- symbolic model checking
- partial order reduction
- bounded model checking
- timed automata
- verification method
- computation tree logic
- process algebra
- transition systems
- pspace complete
- epistemic logic
- formal methods
- finite state machines
- embedded systems
- concurrent systems
- reactive systems
- asynchronous circuits
- artificial intelligence
- abstract interpretation
- deterministic finite automaton