• search
    search
  • reviewers
    reviewers
  • feeds
    feeds
  • assignments
    assignments
  • settings
  • logout

A high throughput CAVLC hardware architecture with parallel coefficients processing for HDTV H.264/AVC enconding.

Fábio Luís Livi RamosBruno ZattThaísa Leal da SilvaAltamiro Amadeu SusinSergio Bampi
Published in: ICECS (2010)
Keyphrases