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Design of Power-Efficient FPGA Convolutional Cores with Approximate Log Multiplier.
Leonardo Tavares Oliveira
Min Soo Kim
Alberto A. Del Barrio García
Nader Bagherzadeh
Ricardo Menotti
Published in:
ESANN (2019)
Keyphrases
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efficient implementation
hardware implementation
user interface
design process
hardware design
neural network
case study
power consumption
design methodology
floating point
single chip
power reduction
hardware architectures
fpga hardware