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An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS.
Xin Zhang
Koichi Ishida
Makoto Takamiya
Takayasu Sakurai
Published in:
ASP-DAC (2011)
Keyphrases
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cmos technology
power dissipation
analog vlsi
high speed
nm technology
low cost
metal oxide semiconductor
silicon on insulator
circuit design
single chip
low power
power consumption
physical design
image sensor
low voltage
random access memory
integrated circuit
neural network