A low power 16-bit 50 MS/s pipeline ADC with 104 dB SFDR in 0.18 μm CMOS.
Xiaodan ZhouWeipeng HeDongbing FuJianan WangGuangbing ChenQiang LiPublished in: Microelectron. J. (2024)
Keyphrases
- low power
- analog to digital converter
- mixed signal
- power consumption
- low cost
- high speed
- image sensor
- single chip
- high power
- vlsi circuits
- logic circuits
- cmos technology
- digital signal processing
- low power consumption
- vlsi architecture
- power reduction
- delay insensitive
- wireless transmission
- cmos image sensor
- hardware and software
- gate array
- real time
- wide dynamic range