Efficient FPGA Floating-Point Multiplier with ATM and XOR-MUX.

S. Sasikumar B. Maheshwar Reddy V. R. Prakash M. Malleshwar Reddy

Published in: ICCCNT (2023)

Keyphrases

floating point
sparse matrices
fixed point
square root
hardware implementation
high speed
signal processing
fast fourier transform
instruction set
interval arithmetic
floating point arithmetic