Folding Memory Shared Processor Array (FMSPA) Architecture for Channel Estimation of Downlink OFDMA IEEE 802.16e System.
Savitri GalihTrio AdionoAdit Kurniawan IskandarPublished in: PARELEC (2011)
Keyphrases
- processor array
- channel estimation
- physical layer
- application layer
- resource allocation
- parallel algorithm
- communication systems
- parallel implementation
- multipath
- bit error rate
- code division multiple access
- wireless channels
- network layer
- wireless communication
- parallel computers
- mesh connected
- communication protocol
- fading channels
- ofdm system
- data transfer
- cross layer
- smart grid
- array processor
- channel coding
- end to end
- video streaming
- maximum likelihood