Memory-efficient TCP reassembly using FPGA.
Tran Huy VuNguyen Quoc TuanTran Ngoc ThinhNguyen Tran Huu NguyenPublished in: SoICT (2011)
Keyphrases
- memory efficient
- high speed
- end to end
- real time image processing
- hardware implementation
- field programmable gate array
- low cost
- external memory
- round trip
- signal processing
- ip networks
- real time
- congestion control
- verilog hdl
- hardware architecture
- flow control
- hardware design
- fpga implementation
- parallel hardware
- single chip
- software implementation
- data acquisition
- video streaming
- iterative deepening
- multiple sequence alignment