Timing error masking by exploiting operand value locality in SIMD architecture.
Jaehyeong SimJun-Seok ParkSeungwook PaekLee-Sup KimPublished in: ICCD (2014)
Keyphrases
- management system
- single instruction multiple data
- processor array
- array processor
- parallel algorithm
- error bounds
- hardware implementation
- massively parallel
- parallel implementation
- real time
- software architecture
- image processing
- parallel processing
- network architecture
- control system
- data structure
- hardware architecture
- processing elements
- layered architecture
- spatial locality
- web services
- mesh connected
- information systems