A 0.47-1.6mW 5bit 0.5-1GS/s time-interleaved SAR ADC for low-power UWB radios.
Pieter HarpeBen BuszeKathleen PhilipsHarmke de GrootPublished in: ESSCIRC (2011)
Keyphrases
- low power
- power consumption
- analog to digital converter
- mixed signal
- single chip
- image sensor
- wireless transmission
- high speed
- communication systems
- low cost
- high power
- vlsi circuits
- vlsi architecture
- nm technology
- cmos technology
- logic circuits
- low power consumption
- digital signal processing
- power dissipation
- delay insensitive
- wide dynamic range