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Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus.

Mai Y. ChingAng T. BoonChin K. YeongFakhrul Zaman Rokhani
Published in: APCCAS (2010)
Keyphrases
  • high speed
  • power dissipation
  • low cost
  • low power
  • power consumption
  • optimization method
  • database
  • optimization problems
  • optimization process
  • phase locked loop