Novel multiple bypass bins scheme for low-power UHD video processing HEVC binary arithmetic encoder architecture.
Fábio Luís Livi RamosBruno ZattMarcelo Schiavon PortoSergio BampiPublished in: SBCCI (2017)
Keyphrases
- low power
- video processing
- video compression
- power consumption
- vlsi architecture
- low cost
- high speed
- power reduction
- real time
- cmos technology
- video analysis
- motion compensation
- signal processing
- low complexity
- video coding
- image processing
- video data
- video segmentation
- vlsi implementation
- motion estimation
- motion compensated
- nm technology
- video codec
- rate distortion
- distributed video coding
- wyner ziv
- video surveillance
- computer vision
- video coding standard
- power dissipation
- macroblock
- logic circuits
- motion vectors