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Reliable and Modeling Attack Resistant Authentication of Arbiter PUF in FPGA Implementation With Trinary Quadruple Response.

Siarhei S. ZalivakaAlexander A. IvaniukChip-Hong Chang
Published in: IEEE Trans. Inf. Forensics Secur. (2019)
Keyphrases
  • neural network
  • fpga implementation
  • hardware implementation
  • multiscale
  • authentication protocol
  • real time
  • artificial intelligence
  • general purpose
  • bit rate