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Low power process, voltage, and temperature (PVT) variations aware improved tunnel FET on 6T SRAM cells.
K. Niranjan Reddy
P. V. Y. Jayasree
Published in:
Sustain. Comput. Informatics Syst. (2019)
Keyphrases
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low power
power consumption
high speed
low cost
wireless transmission
high power
vlsi architecture
logic circuits
low power consumption
cmos technology
digital signal processing
power reduction
delay insensitive
single chip
image processing
room temperature
low voltage
energy dissipation
vlsi circuits