Fast parallel soft Viterbi decoder mapping on a reconfigurable DSP platform.
Amir Hosein KamalizadRichard PlettnerChengzhi PanNader BagherzadehPublished in: SoCC (2004)
Keyphrases
- systolic array
- parallel architecture
- reconfigurable architecture
- texas instruments
- noisy channel
- parallel processing
- digital signal
- real time
- parallel implementation
- distributed memory
- digital signal processor
- signal processing
- low cost
- hidden markov models
- parallel programming
- digital signal processing
- hardware implementation
- parallel computing
- parallel computation
- shared memory
- data flow
- parallel architectures
- viterbi algorithm
- fine grain
- image compression
- coarse grain
- high speed