Energy Efficient In-Memory Binary Deep Neural Network Accelerator with Dual-Mode SOT-MRAM.
Deliang FanShaahin AngiziPublished in: ICCD (2017)
Keyphrases
- energy efficient
- neural network
- wireless sensor networks
- random access memory
- energy consumption
- sensor networks
- design considerations
- associative memory
- data dissemination
- routing protocol
- base station
- data gathering
- multi hop
- multi core architecture
- energy efficiency
- sensor nodes
- parallel implementation
- data transmission
- real time