An FPGA Based Accelerator for SAT Based Combinational Equivalence Checking.
Mona SafarM. Watheq El-KharashiAshraf SalemPublished in: IWSOC (2005)
Keyphrases
- field programmable gate array
- bounded model checking
- answer set programming
- hardware implementation
- sat solvers
- application specific
- version space
- parallel implementation
- embedded systems
- ai planning
- hardware software partitioning
- compute intensive
- constraint solver
- constraint logic programming
- low cost
- hardware architecture
- equivalence relation
- planning domains
- boolean satisfiability
- sat encodings
- answer sets
- knowledge representation