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Folded down-conversion mixer for a 60 GHz receiver architecture in 65-nm CMOS technology.
Najam Muhammad Amin
Zhigong Wang
Zhiqun Li
Published in:
J. Zhejiang Univ. Sci. C (2014)
Keyphrases
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cmos technology
low power
power consumption
spl times
parallel processing
low voltage
high speed
mixed signal
clock frequency
low cost
power dissipation
silicon on insulator
power management
image sensor
network on chip
embedded dram
pattern recognition