A new VLSI architecture for 3D-DCT video compression system.
Jeoong Sung ParkTokunbo OgunfunmiPublished in: SiPS (2013)
Keyphrases
- video compression
- vlsi architecture
- low complexity
- motion estimation
- vlsi implementation
- motion compensation
- low power
- real time
- video coding
- motion compensated
- video data
- video conferencing
- low bit rate
- macroblock
- compression ratio
- motion vectors
- computational complexity
- power consumption
- video codec
- bit allocation
- inter frame
- bit plane
- mode decision
- bit rate
- distributed video coding
- low cost
- image compression
- video coding standard
- computer vision