Login / Signup
Low power motion estimator architecture with leakage power reduction in deep sub-micron SoC.
Gyu-Sung Yeon
Chi-Hun Jun
Tae-Jin Hwang
Seongsoo Lee
Jae-Kyung Wee
Published in:
Circuits, Signals, and Systems (2004)
Keyphrases
</>
low power
power reduction
cmos technology
power consumption
motion estimator
low cost
high speed
power dissipation
motion estimation
digital signal processing
power saving
real time
video compression
low voltage
estimation algorithm
motion field
energy efficiency
video sequences
image processing