High-Speed SC Decoder for Polar Codes achieving 1.7 Tb/s in 28 nm CMOS.
Lukasz LopacinskiAlireza HasaniGoran PanicNebojsa MaleticJesús GutiérrezMilos KrsticEckhard GrassPublished in: VLSI-SoC (2022)
Keyphrases
- high speed
- low power
- reed solomon
- cmos technology
- low density parity check
- error control
- decoding algorithm
- joint source channel
- ldpc codes
- error correction
- nm technology
- turbo codes
- rotation invariant
- focal plane
- error concealment
- low complexity
- rate allocation
- image transmission
- silicon on insulator
- distributed video coding
- frame rate
- fourier transform
- power consumption
- frequency domain
- rate compatible punctured convolutional
- image sequences
- channel coding
- motion estimation