An O(1) time complexity sorting network for small number of inputs with hardware implementation.
Parham Taghinia JelodariMojtaba Parsa KordasiabiSamad SheikhaeiBehjat ForouzandehPublished in: Microprocess. Microsystems (2020)
Keyphrases
- hardware implementation
- small number
- signal processing
- hardware design
- efficient implementation
- pipeline architecture
- fpga implementation
- software implementation
- image processing algorithms
- network size
- real time
- neural network
- hardware architecture
- wireless sensor networks
- computational complexity
- compression ratio
- network structure
- peer to peer
- multiresolution
- dedicated hardware
- machine learning
- communication networks
- parallel architecture
- pattern recognition
- image binarization