Multi-chip phase synchronization circuit of fractional-N PLL.

Yantian Xu Zhiyu Wang Jiarui Liu Hua Chen Faxin Yu

Published in: IEICE Electron. Express (2023)

Keyphrases

phase locked loop
high speed
analog vlsi
circuit design
single phase
chip design
evolvable hardware
power dissipation
cmos technology
real time
data sets
low cost
neural network
evolutionary algorithm
analog circuits
logic circuits