Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking.
Chunsheng LiuVikram IyengarJiangfan ShiÉrika F. CotaPublished in: VTS (2005)
Keyphrases
- network on chip
- power dissipation
- power consumption
- low power
- routing algorithm
- cmos technology
- network simulator
- scheduling problem
- low cost
- multi processor
- interconnection networks
- circuit design
- ibm power processor
- image processing
- design methodology
- high speed
- digital signal processing
- precedence constraints
- finite state machines
- scheduling algorithm