A 10-b 100-MS/s pipelined ADC with an optimized bit-stage resolution in 65nm CMOS technology.
Pasquale DeliziaGianni SaccomannoStefano D'AmicoAndrea BaschirottoPublished in: ISCAS (2010)
Keyphrases
- cmos technology
- spl times
- low power
- analog to digital converter
- mixed signal
- power consumption
- parallel processing
- low voltage
- image sensor
- single chip
- silicon on insulator
- high speed
- power dissipation
- high resolution
- flip flops
- random access memory
- instruction set architecture
- real time
- image processing algorithms
- space time
- image restoration
- image processing