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Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures.
Rakesh Kumar
Keith I. Farkas
Norman P. Jouppi
Parthasarathy Ranganathan
Dean M. Tullsen
Published in:
IEEE Comput. Archit. Lett. (2003)
Keyphrases
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power reduction
power consumption
high speed
low power
power saving
real time
pattern recognition
context aware