Performance Benchmark of DSP and FPGA Implementations of Low-Level Vision Algorithms.
Daniel BaumgartnerPeter RösslerWilfried KubingerPublished in: CVPR (2007)
Keyphrases
- vision algorithms
- low level
- verilog hdl
- digital signal processing
- systolic array
- real time image processing
- signal processing
- high speed
- computer vision systems
- digital signal
- high level
- image interpretation
- hardware architectures
- computer vision algorithms
- higher level
- software implementation
- computer vision
- data flow
- field programmable gate array
- low power
- low level features
- single chip
- low cost
- test bed
- low power consumption
- neural network
- digital signal processors
- image processing
- hardware architecture
- hardware implementation
- embedded systems
- image analysis
- digital signal processor
- real time
- general purpose processors
- efficient implementation