Statistical Model Checking of a Moving Block Railway Signalling Scenario with Uppaal SMC - Experience and Outlook.
Davide BasileMaurice H. ter BeekVincenzo CianciaPublished in: ISoLA (2) (2018)
Keyphrases
- model checking
- model checker
- temporal logic
- formal verification
- timed automata
- formal specification
- finite state
- finite state machines
- automated verification
- temporal properties
- partial order reduction
- verification method
- epistemic logic
- bounded model checking
- transition systems
- computation tree logic
- pspace complete
- symbolic model checking
- asynchronous circuits
- reachability analysis
- concurrent systems
- formal methods
- web services
- linear temporal logic