Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs.
David ZaretskyGaurav MittalRobert P. DickPrith BanerjeePublished in: ISQED (2007)
Keyphrases
- high level synthesis
- parallel architecture
- design space exploration
- scheduling problem
- hardware implementation
- container terminal
- design space
- low cost
- high speed
- real time
- signal processing
- computer vision
- parallel processing
- scheduling algorithm
- parallel machines
- artificial intelligence
- computer architecture
- parallel implementation
- computer systems
- design principles