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Improved Toolchain-Compatible Standard Cells with 5% - 36% Lower EDP for Super Threshold Operation in 65nm Low-Power CMOS Technology.
Shubham Yadav
André B. J. Kokkeler
Mark S. Oude Alink
Published in:
ISCAS (2023)
Keyphrases
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cmos technology
low power
power consumption
low cost
high speed
low voltage
mixed signal
single chip
power dissipation
image sensor
silicon on insulator
low power consumption
digital signal processing
parallel processing
power reduction
random access memory
pattern recognition