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A 3-6GHz 5-to-512 Multiplier Adaptive Fast-Locking Self-Biased PLL in 28nm CMOS.

Binghui WangHaigang YangYiping Jia
Published in: ISCAS (2021)
Keyphrases
  • high speed
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  • database
  • neural network
  • concurrency control
  • hardware implementation
  • power supply
  • cmos technology
  • analog vlsi
  • real time
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  • vlsi circuits