A 3-6GHz 5-to-512 Multiplier Adaptive Fast-Locking Self-Biased PLL in 28nm CMOS.

Binghui Wang Haigang Yang Yiping Jia

Published in: ISCAS (2021)

Keyphrases

high speed
low cost
power consumption
database
neural network
concurrency control
hardware implementation
power supply
cmos technology
analog vlsi
real time
high quality
low power
fine granularity
vlsi circuits