Login / Signup
Performance Analysis of a JPEG Encoder Mapped onto a Virtual MPSoC-NoC Architecture using TLM 2.0.1.
F. A. Escobar-Juzga
F. E. Segura-Quijano
Published in:
J. Circuits Syst. Comput. (2013)
Keyphrases
</>
multi processor
network on chip
decoding process
virtual environment
image coding
fpga implementation
bit rate
rate distortion
image compression
motion estimation
virtual world
compression algorithm
bit allocation
jpeg images
packet switched