Reduced Hardware NOrec: A Safe and Scalable Hybrid Transactional Memory.
Alexander MatveevNir ShavitPublished in: ASPLOS (2015)
Keyphrases
- commodity hardware
- transactional memory
- blue gene
- speculative execution
- parallel computing
- massively parallel
- computing systems
- parallel processing
- cloud computing
- parallel architectures
- hardware design
- hardware implementation
- field programmable gate array
- parallel execution
- real time
- low cost
- high end
- big data
- image processing
- graphics processing units
- address space
- parallel programming
- data analytics
- hardware and software