A new low-power full-adder cell for low voltage using CNTFETs.

K. S. Jitendra Avireni Srinivasulu Brahmadeo Prasad Singh

Published in: ECAI (2017)

Keyphrases

low power
low voltage
cmos technology
power dissipation
logic circuits
power consumption

low cost
high speed
mixed signal
power line
power management
single chip

digital signal processing
low power consumption
vlsi circuits
image sensor
vlsi architecture
gate array

energy saving
energy efficiency
data flow
power reduction
pattern recognition
design considerations