The low power design of SM4 cipher with resistance to differential power analysis.
Yanbo NiuAnping JiangPublished in: ISQED (2015)
Keyphrases
- low power
- single chip
- power consumption
- high speed
- low cost
- low power consumption
- logic circuits
- vlsi architecture
- cmos technology
- digital signal processing
- power dissipation
- power reduction
- mixed signal
- wireless sensor networks
- high power
- power analysis
- gate array
- embedded systems
- design process
- delay insensitive
- ultra low power