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A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC.

Jun DeguchiFumihiko TachibanaMakoto MorimotoMasayoshi ChibaTakeshi MiyabaHideki TanakaKyoichi TakenakaSatoshi FunayamaKunihiko AmanoKazuhide SugiuraRyuta OkamotoShouhei Kousai
Published in: ISSCC (2013)
Keyphrases
  • cmos image sensor
  • single chip
  • dynamic range
  • power consumption
  • synthetic aperture radar
  • signal to noise ratio
  • low power
  • image reconstruction
  • sar images
  • processing capabilities
  • solid state
  • image analysis