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Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution.

David LevacqMuhammad YazidHiroshi KawaguchiMakoto TakamiyaTakayasu Sakurai
Published in: ESSCIRC (2007)
Keyphrases
  • power consumption
  • power saving
  • power dissipation
  • low power
  • energy efficiency
  • energy saving
  • high speed
  • power reduction
  • data center
  • real time
  • social networks