Runtime Verification on FPGAs with LTLf Specifications.
Tommy Tracy IILucas M. TabajaraMoshe Y. VardiKevin SkadronPublished in: FMCAD (2020)
Keyphrases
- concurrent systems
- automated verification
- formal verification
- model checking
- model checker
- bounded model checking
- asynchronous circuits
- delay insensitive
- field programmable gate array
- formal specification
- temporal logic
- protocol specification
- face verification
- verification method
- hardware software
- high level
- functional requirements
- person identification
- real time
- formal analysis
- control flow
- operational semantics
- formal methods
- finite state machines
- distributed systems
- general purpose
- evolutionary algorithm
- genetic algorithm
- neural network
- data sets